Graphene gets written about a lot. The so-called “wonder material” could revolutionize everything from the design of space elevators to cancer drug delivery. Thanks to a recent breakthrough at the University of California, it may also be at the heart of the chips found inside your next generation, super-powerful computer. Right in the place silicon used to be.
The innovation from researchers in electrical and computer engineering at the University of California, Santa Barbara, is all about making a complete integrated circuit design, complete with discrete electronic components and interconnects, on a single flat atom-deep layer of graphene.
So, why do this? As we push silicon-based integrated circuit designs forward, using ever smarter tricks and techniques to fashion more, smaller transistors onto a chip–boosting its computing power and reducing power consumption–scientists are bumping up against the laws of physics. One of the big limiting factors in future silicon chip design is contact resistance. This is different from the usual linear resistance to electrical current flow you think of when you think of a piece of wire or, ahem, a resistor. It’s extra resistance caused when parts of a component touch each other, or a component is touching an interconnecting wire, such as a semiconductor transistor connected to a metal interconnect. Essentially it saps just a little bit of energy from the current flowing across the connection and introduces some noise into the current–and in most cases it’s not a problem. When you’ve got billions of transistors and interconnects on a chip, however, those little bits of energy quickly add up. And as you cram smaller components more densely onto a silicon chip, things get worse.
This is where graphene comes in. Since you can adjust the properties of graphene to act as both a metal-like interconnect and as a semiconductor component like a transistor, you could theoretically fashion an entire integrated circuit onto a sheet of graphene and more or less avoid any contact resistance issues whatsoever.
The team at UC Santa Barbara have worked out how to etch narrow and wide circuit patterns into a sheet of graphene–acting as components and interconnects–and then use deposition techniques to layer actual graphene-based transistors on the top. Their proposed circuits have 1.7 times higher noise margins, and 10 to 100 times less power loss compared to typical CMOS chip tech. Though the chip is just a theoretical concept at the moment, breakthroughs happening around the world are very likely to make its production possible very soon.
The upshot of this sort of tech could be more powerful chips that eat less power, and thanks to the properties of graphene itself, it could even mean regular chip designs that consume amazingly low power, or flexible and transparent computer systems. Remember us asking at FastCoLabs “if the walls could compute?” Yup, your graphene-embedded wallpaper could be a computer.
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