Every few years the end of Moore’s law (predicting the ever-shrinking, ever-more-powerful design of silicon chips) is predicted, and then a new breakthrough is achieved that enables more shrinkage of the components of CPUs and other chips. The result is always our latest and greatest clutch of CPUs, memory devices and silicon what-nots that are more powerful than the last ones, while consuming less electricity and generating less heat. Some limits are approaching though that do signify the upper-end of Moore’s applicability, since they run into hard physics limitations–and the way that chips are currently crafted have proved particularly irksome for makers of flash-based memory.
Which makes a discovery by a Rice University science group all the more interesting: It uses a new technique on an existing chip-fabbing component, silicon dioxide. The 5-nanometer nanocrystal “wires” the system relies on were first discovered in the 1960s, but engineers lacked the skills to manipulate such small-scale phenomenon then. Nowadays nanotech is becoming common, and Rice’s team discovered that under certain conditions when you apply the charge from a tiny handful of electrons to a silicon dioxide nanowire, you can form a temporary localized defect in its crystal structure. This allows fabricators to easily reconnect the crystal lattice. In other words, the nanowire acts as a reversible single-bit storage unit. Scale this up over millions of nanowires, and you’d get a “chip” that acts just like a typical flash memory unit–only much more densely-packed, and potentially more reliable thanks to the physical resilience of silicon dioxide.
Test devices capable of storing mere thousands of bits have already been fabricated, and this is long before the kind of scaling-up you’d see in a commercial fab endeavor. Better yet, the technology is extremely capable of stacking up in three dimensions–this kind of 3-D chip trick has been increasingly an option for chip designers desperate to cram more and more transistors into a small space on a CPU die, but the manufacturing processes needed for layered chips are tricky. Rice’s breakthrough promises more simple 3-D packing.
And this has one big pay-off: Mobile devices will be able to squeeze in more storage in a smaller space–and this is the intriguing one–smaller devices will be able to get meaningful-sized storage capabilities, which is important when you combine them with shrinking processors. Think tiny earpiece-sized cellphones, or wristwatch supercomputers and you begin to see how exciting this could get.
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